1. Field of the Invention
This invention relates generally to the structure and fabrication process of semiconductor transistors. More particularly, this invention relates to a novel and improved structure and manufacture process for a high density shallow junction semiconductor power device which has improved punch through prevention characteristics, maintaining a low JFET resistance, achieving higher switching speed while manufactured with a process flow without requiring the use of a polysilicon mask for one of the preferred embodiments.
2. Description of the Prior Art
The requirement to allow extra width to compensate for potential misalignment errors in power transistor manufacture often becomes a major difficulty in an effort to reduce the critical dimensions in order to make power transistors of higher density. In addition to the difficulties caused by the alignment imprecision, there are several other technical difficulties now encountered by those of ordinary skill in the art. Specifically, the dimensions of the polysilicon layer between the cells are shrunk when the cell density is increased. The shrinking dimensions of a polysilicon layer, i.e., the reduction in widths of the polysilicon gates, between the cells often generates a higher JFET resistance. In order to deal with the increased JFET resistance for a power device with higher cell density, shallow junctions are formed for the semiconductor power device. A semiconductor power device of shallow junction is however subject to a potential punch through problem. Damages to device may arise to a shallow junction device when a punch through occurs even such device can provide the advantage that the JFET resistance is reduced. Various structure features are implemented as will be discussed below to prevent the occurrence of a punch through. However, such punch through prevention features often lead to increase in JFET resistance, particularly for devices where the cell sizes are further reduced.
These technical difficulties cannot be conveniently resolved as illustrated by many prior art patents where attempts are made to solve one problem while causing other related problems to become worse. Further reduction of cell size to increase the cell density for the semiconductor power devices seems to be hindered by several related technical concerns. Unless these related difficulties can be effectively resolved, product reliability problems and device malfunctions caused by these difficulties would limit our capability to manufacture the semiconductor power device with higher density than which have been now achieved.
In U.S. Pat. No. 5,479,037 entitled "Low Threshold Voltage Epitaxial DMOS Technology" Hshieh et al. disclose a threshold power DMOS transistor structure which has a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon (referring to FIG. 1). The lightly doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch through susceptibility due to non-uniformity in epitaxial doping concentration. A relatively heavy doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer is located below the channel region to reduce the drain to source resistance. Because the heavily doped epitaxial region is located below the channel region and not in the regions of the structure mostly susceptible to body region punch through, the deep heavily doped regions would not cause the threshold voltage variations.
Even that advantages of low threshold voltage and punch through prevention can be achieved by lightly doping a epitaxial shallow layer for a DMOS device, Hshieh's DMOS formed on a substrate with shallow lightly doped epitaxial layer leads to another difficulty when the DMOS cell density is further increased. When the DMOS cells are being placed closer to each other, the lightly doped epitaxial layer causes the JFET resistance to increase due to the smaller JFET regions between the cells which are now manufactured with a lower dopant concentrations. The usefulness of this DMOS structure with lightly doped epitaxial layer is limited due to this difficulty when the cell size is further reduced with increased cell density.
In U.S. Pat. No. 5,404,040 entitled "Structure and Fabrication of Power MOSFET Including Termination Structure", (issued on Apr. 4, 1995) Hshieh et al. disclose a semiconductor power MOSFET device having a main active area and a peripheral termination area. The power MOSFET includes a first insulating layer of substantially uniform thickness lies over the active and termination areas. The main polycrystalline portion lies over the first insulating layer largely above the active area. A first and a second peripheral polycrystalline segments lie over the first insulating layer above the termination area. A gate electrode contacts the main polycrystalline portion. A source electrode contact the active area, the termination area and the first polycrystalline segment. An optional additional metal portion contacts the second polycrystalline segments. The power MOSFET is manufactured by a five mask process. This device provides a unique termination structure for a power MOSFET by dividing the device into a main active area and a peripheral termination area and the first insulating layer is of substantial uniform thickness of about 100-1000 Angstroms overlies the termination and the active area. Due to this thin oxide layer structure, particularly underneath the field plate, the MOSFET device may encounter a walk-out problem when the voltage applied to the field plate exceed a certain limit. Furthermore, this thin oxide layer between two peripheral polycrystalline silicon segments may be incidentally etched away in the manufacture process. A reliability problem may be induced when the etch process is not very precisely controlled. The production costs are increased due to this special manufacture precision requirement.
Therefore, a need still exists in the art of power device structure and fabrication to provide a new device structure and manufacturing method, particularly to those engaged in semiconductor power device design and fabrication of higher cell density to resolve these difficulties and limitations. It is desirable that the novel device structure and fabrication method can be implemented with self-aligned and automatic process-adjusted body regions such that the novel structure would enable those of ordinary skill in the art to further reduce the cell size to achieve higher cell density. In the meantime, it is also desirable that while overcoming these limitations and difficulties, cost savings and better reliability can be achieved when simplified manufacture process with less number of masks when the novel structure and manufacture processes are implemented.